This application relies for priority upon Korean Patent Application No. 99-45012, filed on Oct. 18, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a semiconductor device where variations in a gate critical dimension (hereinafter referred to as gate CD) are reduced, regardless of the arrangement directions of gate electrodes in transistors of one chip.
In general, the size of a semiconductor device decreases as the degree of integration increases, particularly when the degree of integration relates to an integrated circuit in which the gate CD of gate electrodes has also been reduced. Accordingly, as it is highly probable that there may be variations in the length of the gate electrodes in even one chip, it becomes more and more important to make the channel length of the gate electrodes exactly equal.
FIG. 1 shows exemplary views of gate electrodes in a general semiconductor device. As shown in FIG. 1, a first gate electrode 11 is generally formed having a length L1 along an x-axis in longitudinal direction parallel to a channel. Similarly, a second gate electrode 12 is generally formed having a length L2 along a y-axis in a longitudinal direction parallel to another channel on the same chip substrate 10. Furthermore, although only one example is presented for each of the first and second gate electrodes 11 and 12 in FIG. 1, it should be taken for granted that larger numbers of the first and second gate electrodes 11 and 12 are actually formed on the same chip.
In order to make the gate lengths L1, L2 equal on the same substrate 10, identical size of patterns should be formed for the first and second gate electrodes 11 and 12 on a photo mask (not shown) used to create the gate electrodes 11 and 12. However, if the gate lengths L1, L2 are reduced below about 0.2 xcexcm, there may be variations in the gate CD of the first and second gate electrodes 11 and 12 formed on the same substrate 10. This may happen because there is a skew between the first and second gate electrodes made by parameters such as the mask, the photo scanning direction, or the directional characteristics of the etching process involved in the formation of the gate electrodes.
If such variations are not adjusted, the gate CD of the first and second gate electrodes respectively having the gate lengths L1, L2 on the same chip may be divided into two values of L11 and L12 as in the normal distribution curves shown in FIG. 2. As FIG. 2 shows, the distribution for L12 indicates higher values for the gate length L12 than for gate length L11.
In particular, the reference letters L1, and L2 represent target values or set values in the gate length, while reference letters L11 and L12 represent the central value or representative value in the gate CD measured.
In other words, if the gate CD of the gate length L1 is regarded as a desired value, the gate CD of the gate length L2 is larger than the desired value. On the other hand, if the gate CD of the gate length L2 is regarded as a desired value, the gate CD of the gate length L1 is smaller than the desired value. Regardless, there may be false operational effects of transistors because the gate CD of one of the gate lengths is larger or smaller than the desired value.
This is particularly important in a sub-quarter micron semiconductor device like a high speed CPU or a logic element, since a minimum variation in the gate CD of the gate lengths may result in significant deterioration in both the performance and yield of such semiconductor device products.
For instance, if the gate CD is larger than the desired value, then the effective channel length of gate electrodes increases, the threshold voltage Vth of the related transistor increases, the drain saturation current of the transistor decreases, and the drive-in current of the transistor decreases. Such changes result in a loss of the transistor properties and a reduction in the operational speed of the high speed CPU or the logic element that make up the relevant device.
On the other hand, if the gate CD is smaller than the desired value, the threshold voltage of the related transistor decreases, the drain saturation current of the transistor increases, the current leakage, i.e., the OFF current, of the transistor increases, and the breakdown voltage of the transistor decreases. Such changes result in operational failures and, even worse, a reduction in the yield of a semiconductor device such as a high speed CPU or logic element.
At present, a variety of methods have been developed to minimize the variations in the gate CD of the gate length of gate electrodes on the same chip, such as inducing a change in the gate electrode forming material, making a hard mask onto the gate electrodes, changing the type or thickness of a photo resist layer, making a change in the conditions of an etching process used to form gate electrodes, and adding a side optical proximity correlation depending on the pattern density of the gate electrodes, i.e., using a so-called photo mask process.
Specifically, the method of causing a change in the material for making gate electrodes includes changing a condition for making a deposition structure of a polysilicon layer. As a result, gate electrodes are formed of different particle sizes as compared to the polysilicon layer. This can smooth the morphology of particles of the polysilicon layer and reduce the thickness of the polysilicon layer.
The method of making a hard mask onto the gate electrodes includes depositing a hard mask, such as a thin oxide or nitride layer, on the polysilicon layer, selectively etching the hard mask with a pattern of a photo resist layer, and finally forming gate electrodes by further etching the polysilicon layer with a remaining hard mask.
In the method of making a change in the type of the photo resist layer, a negative or positive photo resist layer is used to increase or decrease the resistance of the photo resist layer, or to reduce the thickness of the photo resist layer.
The method of changing conditions in the process of etching the gate electrodes includes, for example, changing the conditions for performing a selective etching process of the polysilicon layer.
On the other hand, since the variations in the gate CD of gate electrodes are significantly different depending on the pattern density, there is also another conventional method, a so-called selective biasing method, in which a selective biasing process is performed depending on the pattern density. However, there is a disadvantage in the selective biasing method in that the variations in the gate CD of gate electrodes cannot be adjusted due to some directional characteristics of the pattern arrangements.
Therefore, it is an object of the present invention to provide a method for fabricating a semiconductor memory device by which variations in gate CD of gate electrodes decrease regardless of the arrangement directions of the gate electrodes.
In order to accomplish the aforementioned object of the present invention, a method is provided for fabricating a semiconductor device. This method includes forming original first and second gate electrodes on a substrate in longitudinal directions parallel to first and second channels in different arrangement directions, measuring first and second lengths of the first and second original gate electrodes, respectively, forming an adjusted photo mask, the adjusted photo mask having adjusted patterns patterns corresponding to the first and second original gate electrodes, adjusted on the basis of the measured first and second lengths, and forming adjusted first and second gate electrodes on the substrate via the adjusted photo mask.
The forming of the adjusted photo mask may further comprise comparing the measured first and second lengths, and estimating a mask bias on the basis of the difference between the first and second lengths. The measured first and second lengths may be compared with a desired value. This desired value may be the second length.
The adjusted photo mask is preferably formed to reduce the length of the adjusted first gate electrode if the length of the original first gate electrode is larger than a desired value. Similarly, the adjusted photo mask is preferably formed to increase the length of the adjusted first gate electrode if the length of the original first gate electrode is smaller than a desired value.
The length of the adjusted first and second gate electrodes can be varied by using a push bias process, a phase shift process, or the like.
The adjusted photo mask may be formed by increasing the length of a selected one of the original first and second gate electrodes formed via an original photo mask if the length of the selected gate electrode is smaller than a desired value.
The length of the selected gate electrode can be varied by using a push bias process or a phase shift process. The first and second gate electrodes preferably comprise a polysilicon layer. In addition, the adjusted first and second gate electrodes have substantially the same length.
As a result of this, gate electrodes having an identical gate CD can be formed on the same substrate regardless of the different arrangement directions of the gate electrodes in parallel to channels.